1. Field of the Invention
The present invention relates to a multi-port type semiconductor memory having multi-ports consisting of a plurality of ports for writing and reading data.
2. Description of the Related Art
FIG. 1 is a view of an example of a multi-port type memory cell having a plurality of ports for writing and reading data. As shown in FIG. 1, the multi-port type memory cell of this example is a one-writing port two-reading port type memory cell having a writing port consisting of transistors TWL1, TWL2, TWR1, and TWR2, a first reading port RPT1 consisting of transistors TR11 and TR12, and a second reading port RPT2 consisting of transistors TR21 and TR22.
In the writing port, the gates of the transistors TWL1 and TWR1 are connected in common to a write word line WLW, and the drains are connected to nodes N1 and N2. The gates of the transistors TWL2 and TWR2 are respectively connected to write bit lines BLW1 and BLW2, and the drains are connected to sources of the transistors TWL1 and TWL2. The sources of the transistors TWL2 and TWR2 are both connected to the ground line.
When writing, the write word line WLW is activated by a decoder (not shown) to, for example, be held at a high level. As a result, the transistors TWL1 and TWR1 are turned on (made conductive). The on/off state of the transistors TWL2 and TWR2 are controlled according to the potential of the write bit lines BLW1 and BLW2. As a result, the potentials of the nodes N1 and N2 are set at a high level or low level.
The potential levels of the memory nodes N1 and N2 set by the write operation are held by latch circuits. The states thereof are maintained as they are until the levels can be changed by the next write operation.
At the reading port RPT1, the gate of the transistor TR11 is connected to the reading word line WLR1, a first diffusion layer is connected to the read bit line BLR1, and a second diffusion layer is connected to a first diffusion layer of the transistor TR12. The gate of the transistor TR12 is connected to the node N1, and a second diffusion layer thereof is connected to the ground line. At the reading port RPT1, in response to application of a read pulse signal to the reading word line WLR1, a signal corresponding to the level of the node N1 is read out to the read bit line BLR1.
At the reading port RPT2, the gate of the transistor TR21 is connected to the reading word line WLR2, a first diffusion layer is connected to the read bit line BLR2, and a second diffusion layer is connected to a first diffusion layer of the transistor TR22. The gate of the transistor TR22 is connected to the node N2, and a second diffusion layer thereof is connected to the ground level. At the reading port RPT2, in response to application of a read pulse signal to the reading word line WLR1, a signal corresponding to the level of the node N2 is read out to the read bit line BLR1.
The memory cell shown in FIG. 1 is connected to one write word line WLW, two reading word lines WLR1 and WLR2, two write bit lines BLW1 and BLW2, and two read bit lines BLR1 and BLR2.
FIG. 2 is a view of the configuration of a memory cell MC, a write circuit 4, a first read circuit 2, and a second read circuit 3 in a multi-port type memory consisting of the memory cell shown in FIG. 1.
As shown in FIG. 2, the write bit lines BLW1 and BLW2 and the read bit lines BLR1 and BLR2 are respectively connected via a column selecting circuit 1 to the write circuit 4 and the read circuits 2 and 3.
The column selecting circuit 1 is configured by transfer gates TGR1, TGR2, TGW1, and TGW2. Note that these transfer gates are controlled by a column decoder which is not shown. The column decoder turns the transfer gates on and off in response to a column address signal.
The read circuit 2 is formed by a pMOS transistor PT1 and an inverter INVR1. The source and the drain of the pMOS transistor PT1 are connected respectively to a line supplying a power supply voltage V.sub.DD and the transfer gate TGR1, while the gate is connected to an input terminal of a precharge control signal Pr. An input terminal of the inverter INVR1 is connected to the transfer gate TGR1, and an output terminal is connected to an output terminal of a read data D.sub.01.
The read circuit 3 is formed by a pMOS transistor PT2 and an inverter INVR2. The source and the drain of the pMOS transistor TR2 are connected respectively to the line supplying the power source voltage V.sub.DD and a transfer gate TGR2, while the gate is connected to the input terminal of the precharge control signal Pr. An input terminal of the inverter INVR2 is connected to the transfer gate TGR2, and an output terminal is connected to an output terminal of the read data D.sub.02.
The write circuit 4 is formed by buffers BUF1 and BUF2 and an inverter INVR. An input terminal of the buffer BUF1 is connected to an input terminal of write data D.sub.IN, while an output terminal is connected to the transfer gate TGW1. An input terminal of the inverter INVR is connected to an input terminal of the write data D.sub.IN, an output terminal is connected to an input terminal of the buffer BUF2, and an output terminal of the buffer BUF2 is connected to the transfer gate TGW2.
When writing, the write data D.sub.IN is input via the write circuit 4 to write bit lines BLW1 and BLW2. At this time, the transfer gates TGW1 and TGW2 in the column selecting circuit 1 are turned on by the column decoder. Accordingly, the write data D.sub.IN is input to the writing port WPT. In response to the application of the writing pulse signal to the write word line WLW, data on the write bit lines BLW1 and BLW2 are written in a memory cell MC. As a result of this write operation, levels of the memory nodes N1 and N2 are set in response to the write data D.sub.IN and maintained by latch circuits.
When reading, first, the precharge control signal Pr is held at the low level. In response to this, the pMOS transistors PT1 and PT2 in the read circuits 2 and 3 are turned on, therefore both of the read bit lines BLR1 and BLR2 are precharged, for example, to the level of the power supply voltage V.sub.DD. After the precharging, in response to the application of the reading pulse signal to the read word lines WLR1 and WLR2, a signal corresponding to the level of the memory nodes N1 and N2 in the memory cell is read out by the reading ports RPT1 and RPT2 to the read bit lines BLR1 and BLR2.
For example, when the potential of the node N1 is held at the high level and the node N2 at the low level, the transistor TR12 in the reading port RPT1 is turned on. Accordingly, the read bit line BLR1 is discharged, for example, to the ground potential GND. On the other hand, at the reading port RPT2, the transistor TR22 is turned off (made nonconductive), therefore the read bit line BLR2 is maintained at the precharged potential.
At this time, the transfer gate TGR1 or TGR2 in a column selecting circuit 1 is turned on by the column decoder, therefore the signal on the read bit lines BLR1 and BLR2 is transferred to the read circuit 2 or 3 and read out by these read circuits as data D.sub.01 or D.sub.02, respectively.
At a read operation, it is possible for the reading ports RPT1 and RPT2 to operate simultaneously as well as separately.
FIG. 3 is a view of the overall configuration of a semiconductor memory.
As shown in FIG. 3, the semiconductor memory device comprises row decoders 10, 20, and 30, a memory array 40, a control circuit 50, first and second column decoders 60 and 70, a first column selecting circuit 80, a first sense amplifier 90, a first output circuit 100, a second column selecting circuit 110, a second sense amplifier 120, a second output circuit 130, and a write circuit 140.
The row decoder 10 receives a read address RADR1, selects one of the read word lines WLR11, WLR21, . . . , WLRN1 in response to the received read address, and activates the selected word line, for example, to maintain the selected word line at the high level.
The row decoder 30 receives a read address RADR2, selects one of the reading word lines WLR12, WLR22, . . . , WLRN2 in response to the received read address, and activates the selected word line.
The row decoder 20 receives a write address RADR, selects one of the writing word lines WLW12, WLW22, . . . , WLWN2 in response to the received write address, and activates the selected word line.
The memory array 40 comprises, for example, M.times.N number of memory cells consisting of MC.sub.11, . . . , MC.sub.1M, MC.sub.21, . . . , MC.sub.2M, . . . , MC.sub.N1, . . . , MC.sub.NM arranged in a matrix as shown in FIG. 3 and connected to read word lines, write word lines, read bit lines, and write bit lines.
Note that the configuration of each memory cell MC.sub.11, . . . , MC.sub.1M, MC.sub.21, . . . , MC.sub.2M, . . . , MC.sub.NN1, . . . , MC.sub.NM is the same as that of the memory cell shown in FIG. 1.
The control circuit 50, in response to a read signal RD and a write signal WR input from outside the semiconductor memory, outputs read enable signals RENB1 and RENB2 to sense amplifiers 90 and 120 and a write enable signal WENB to the write circuit 140, respectively.
A column decoder 60 (CLD1) receives a read address RADR1 and controls a column selecting circuit 80 in response to the received read address RADR1. For example, the column decoder 60 selects a transfer gate in the column selecting circuit 80 in response to a column address of a read address signal RADR1 and turns on the selected transfer gate.
A column decoder 70(CLD2) receives a write address WADR and controls a column selecting circuit 110 in response to the received write address WADR. For example, the column decoder 70 selects a transfer gate in the column selecting circuit 110 in response to a column address in write address signal WADR and turns on the selected transfer gate.
The signal selected by the column selecting circuit 80 is detected by a sense amplifier 90, and the detected result is output via an output circuit 100 outside of the semiconductor memory as read data D01.
In the same way, the signal selected by the column selecting circuit 110 is detected by a sense amplifier 120, and the detected result is output via an output circuit 130 outside the semiconductor memory as read data D02.
Write data DIN is input via the write circuit 140 and selected by the column selecting circuit 110. The selected data is input to the predetermined memory cell and stored there.
In the semiconductor memory cell shown in FIG. 3, at the time of a write operation, a predetermined word line is selected from among the write word lines WLW1, WLW2, . . . , WLWN by the row decoder 20 in response to a write address signal WADR and activated. A column selecting circuit 110 is controlled by the column decoder 70, and a predetermined transfer gate is turned on. As a result, write data DIN input through the write circuit 140 is selected by the column selecting circuit 110 and is written in a memory cell selected by the row decoder 20.
During the read operation, in response to read address signals RADR1 or RADR2, the predetermined word line is selected from the read word lines WLR11, WLR21, . . . , WLRN1 by the row decoder 10 or 30 and activated.
The stored data in the memory cells connected to the selected read word line is read out by the reading port to the read bit line selected by the column selecting circuit 80 and output outside of the semiconductor memory as the read data D01 and D02.
The above semiconductor memory requires two write bit lines and two read bit lines per bit and thus requires four bit lines in total per bit. Therefore, when forming a memory array of N number of words and M number of bits, 4M number of bit lines are required. The number of read bit lines is therefore large. It consequently suffers from the disadvantage that the size of the memory array becomes large. Also, along with the increase of the number of the bit lines, the power consumption becomes large due to the data setting and the precharging during the write and read operations.
In the above structure of a memory cell, the number of the read ports can be easily increased by providing additional pairs of nMOS transistors consisting reading ports, read word lines, and bit lines. When the number of the read ports is set to K, (K+2).times.M number of bit lines are required. A large increase of the number of bit lines is therefore inevitable.